An Energy-Efficient Approximate Dadda Multiplier using Almost Full Adders, Majority-Logic 4:2 Compressors, and Clock Gating
Keywords:
4:2 compressor, Approximate computing, Dadda multiplier, Image compression, Low-power design, Majority logicAbstract
Approximate computing has emerged as a key strategy for energy-efficient very large scale integration design, particularly in signal-processing and multimedia applications where modest reductions in arithmetic accuracy are acceptable in exchange for substantial savings in power and delay. This paper presents a low-power 8×8 approximate Dadda multiplier built from approximate, almost-full adders and majority-logic-based 4:2 compressors. The almost full adder reduces transistor count and switching activity relative to a conventional full adder, while the majority-logic 4:2 compressor simplifies the compressor structure and shortens the critical path during partial-product reduction. A modified Dadda reduction format is introduced to lower the maximum output delay and to decrease the number of MOSFETs required compared with conventional Dadda and Wallace-tree multipliers. To improve energy efficiency further, a clock-gating technique is incorporated to suppress unnecessary switching activity in idle portions of the circuit. The design is implemented in Verilog HDL and verified using the Xilinx Vivado Design Suite. Simulation results confirm correct functionality together with reduced propagation delay, lower hardware complexity, and an improved power-delay product, establishing the architecture as well-suited to error-tolerant DSP, image-processing, and edge-computing applications.
References
V. Gupta, D. Mohapatra, A. Raghunathan and K. Roy, “Low-power digital signal processing using approximate adders,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 124–137, Jan. 2013.
S. Mittal, “A survey of techniques for approximate computing,” ACM Computing Surveys, vol. 48, no. 4, pp. 1–33, Mar 2016.
S. Venkatachalam and S. -B. Ko, “Design of power and area efficient approximate multipliers,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 5, pp. 1782–1786, May 2017.
A. Momeni, J. Han, P. Montuschi and F. Lombardi, “Design and analysis of approximate compressors for multiplication,” in IEEE Transactions on Computers, vol. 64, no. 4, pp. 984–994, Apr. 2015.
M. H. Moaiyeri, F. Sabetzadeh, and S. Angizi, “An efficient majority-based compressor for approximate computing in the nano era,” Microsystem Technologies, vol. 24, pp. 1589–1601, 2018.
O. Akbari, M. Kamal, A. Afzali-Kusha and M. Pedram, “Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1352–1361, Apr. 2017.
M. Ha and S. Lee, “Multipliers with approximate 4–2 compressors and error recovery modules,” in IEEE Embedded Systems Letters, vol. 10, no. 1, pp. 6–9, Mar. 2018.
R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1079–1090, Jul. 1997.
C.-H. Chang, J. Gu and M. Zhang, “Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 10, pp. 1985–1997, Oct. 2004.
Z. Yang, J. Han and F. Lombardi, “Approximate compressors for error-resilient multiplier design,” 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), Amherst, MA, USA, 2015, pp. 183–186.
V. Leon, S. Xydis, D. Soudris, and K. Pekmestzi, “Energy-efficient VLSI implementation of multipliers with double LSB operands,” IET Circuits, Devices & Systems, vol. 13, no. 6, pp. 816–821, Sep. 2019.
V. Leon, G. Zervakis, S. Xydis, D. Soudris, and K. Pekmestzi, “Walking through the energy-error Pareto frontier of approximate multipliers,” IEEE Micro, vol. 38, no. 4, pp. 40–49, Jul./Aug. 2018.
A. Gorantla and Deepa P., “Design of approximate compressors for multiplication,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 13, no. 3, pp. 1–17, Apr. 2017.
K. C. Pathak et al., “An efficient Dadda multiplier using approximate adder,” 2020 IEEE Region 10 Conference (TENCON), Osaka, Japan, 2020, pp. 176–181.
A. G. M. Strollo, E. Napoli, D. De Caro, N. Petra and G. D. Meo, “Comparison and extension of approximate 4-2 compressors for low-power approximate multipliers,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 3021–3034, Sept. 2020.
