Machine Learning-based Power Estimation and Fault Detection in VLSI Circuits
Keywords:
Classification, Fault detection, Machine learning, Power estimation, Regression, VLSIAbstract
This study explores the application of Machine Learning (ML) techniques in the domain of Very Large-Scale Integration (VLSI) circuits, specifically focusing on power estimation and fault detection. Traditional methods of power estimation and fault detection require extensive simulations and manual inspections, making them time-consuming and computationally expensive. This study proposes a data-driven approach utilizing ML models to predict power dissipation and classify faulty circuits efficiently. A dataset with key VLSI parameters, such as transistor count, clock frequency, voltage, temperature, current, power dissipation, propagation delay, fanout, and noise margin, is generated and analyzed. Two ML models, a linear regression model for power estimation and a decision tree classifier for fault detection, are implemented and evaluated. The results demonstrate that ML-based techniques provide an efficient and accurate alternative to conventional VLSI analysis methods.
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