LUKKA REENA MADHURI; NAVUDU HEMA GOPIKA DEVI; MUKKU MADHAVI; PANCHUMARTHI JAYAPRIYANKA; AKULA MALLAIAH. Design and Implementation of a High-Performance 128-Bit Arithmetic Logic Unit Using Carry Look Ahead Adder, Vedic Multiplier, and Radix-2 Restoring Division. Advance Research in Analog and Digital Communications, [S. l.], p. 29–45, 2026. Disponível em: https://matjournals.net/engineering/index.php/ARADC/article/view/3313. Acesso em: 5 jul. 2026.